Simple (one byte) instructions
==============================
 INCA, DECA, INCX, DECX, SHL, SHR, ROLC, RORC, SETIM, CLRIM, NOP,
 HALT, POPA, PUSHA, POPSR, PUSHSR

Arithmetic instructions (ADD, ADDC, SUB, SUBC)
==============================================
  - immediate addressing ADD $76:
    1) load operand to B
    2) increment PC
    3) do arithmetic operation
    4) update C, Z, N, O flags

  - absolute addressing ADD [$1234]:
    1) load 1st operand to TPCA HI
    2) increment PC
    3) load 2nd operand to TPCA LO
    4) increment PC
    5) do arithmetic operation
    6) update C, Z, N, O flags

  - indexed addressing ADD [$1234, X]:
    1) load 1st operand to TPCA HI
    2) increment PC
    3) load 2nd operand to TPCA LO
    4) increment PC
    5) do arithmetic operation
    6) update C, Z, N, O flags

Logic instructions (AND, OR, XOR)
=================================
  - immediate addressing OR $76:
    1) load operand to B
    2) increment PC
    3) do logic operation
    4) update Z, N flags

  - absolute addressing OR [$1234]:
    1) load 1st operand to TPCA HI
    2) increment PC
    3) load 2nd operand to TPCA LO
    4) increment PC
    5) do logic operation
    6) update Z, N flags

  - indexed addressing OR [$1234, X]:
    1) load 1st operand to TPCA HI
    2) increment PC
    3) load 2nd operand to TPCA LO
    4) increment PC
    5) do logic operation
    6) update Z, N flags

CMPA instruction
================
  - immediate addressing CMPA $76:
    1) load operand to B
    2) increment PC
    3) update C, Z flags

  - absolute addressing CMPA [$1234]:
    1) load 1st operand to TPCA HI
    2) increment PC
    3) load 2nd operand to TPCA LO
    4) increment PC
    5) update C, Z flags

  - indexed addressing CMPA [$1234, X]:
    1) load 1st operand to TPCA HI
    2) increment PC
    3) load 2nd operand to TPCA LO
    4) increment PC
    5) update C, Z flags

LDA instruction
===============
  - immediate addressing LDA $12:
    1) load operand to ACC
    2) increment PC
    3) update Z, N flags

  - absolute addressing LDA [$1234]:
    1) load 1st operand to TPCA HI
    2) increment PC
    3) load 2nd operand to TPCA LO
    4) increment PC
    5) load ACC using TPCA as address
    6) update Z, N flags

  - indexed addressing LDA [$1234, X]:
    1) load 1st operand to TPCA HI
    2) increment PC
    3) load 2nd operand to TPCA LO
    4) increment PC
    5) load ACC using TPCA + X as address
    6) update Z, N flags

  - indirect addressing LDA [[$1234]]:  
    1) load 1st operand to TPCA HI
    2) increment PC
    3) load 2nd operand to TPCA LO
    4) load TPCB HI using TPCA as address
    5) increment TPCA
    6) load TPCB LO using TPCA as address
    5) load ACC using TPCB as address
    6) update Z, N flags

  - pre-indexed indirect addressing LDA [[$1234, X]]:
    1) load 1st operand to TPCA HI
    2) increment PC
    3) load 2nd operand to TPCA LO
    4) load TPCB HI using TPCA+X as address
    5) increment TPCA
    6) load TPCB LO using TPCA+X as address
    7) load ACC using TPCB as address
    8) update Z, N flags

  - indirect post-indexed addressing LDA [[$1234], X]:
    1) load 1st operand to TPCA HI
    2) increment PC
    3) load 2nd operand to TPCA LO
    4) load TPCB HI using TPCA as address
    5) increment TPCA
    6) load TPCB LO using TPCA as address
    7) load ACC using TPCB + X as address
    8) update Z, N flags

STA instruction
===============
  - absolute addressing STA [$1234]:
    1) load 1st operand to TPCA HI
    2) increment PC
    3) load 2nd operand to TPCA LO
    4) increment PC
    5) store ACC using TPCA as address
    
  - indexed addressing STA [$1234, X]:
    1) load 1st operand to TPCA HI
    2) increment PC
    3) load 2nd operand to TPCA LO
    4) increment PC
    5) store ACC using TPCA + X as address

  - indirect addressing STA [[$1234]]:  
    1) load 1st operand to TPCA HI
    2) increment PC
    3) load 2nd operand to TPCA LO
    4) load TPCB HI using TPCA as address
    5) increment TPCA
    6) load TPCB LO using TPCA as address
    5) store ACC using TPCB as address

  - pre-indexed indirect addressing STA [[$1234, X]]:
    1) load 1st operand to TPCA HI
    2) increment PC
    3) load 2nd operand to TPCA LO
    4) load TPCB HI using TPCA+X as address
    5) increment TPCA
    6) load TPCB LO using TPCA+X as address
    7) store ACC using TPCB as address

  - indirect post-indexed addressing STA [[$1234], X]:
    1) load 1st operand to TPCA HI
    2) increment PC
    3) load 2nd operand to TPCA LO
    4) load TPCB HI using TPCA as address
    5) increment TPCA
    6) load TPCB LO using TPCA as address
    7) store ACC using TPCB + X as address

Big load instructions (BLDIV, BLDSP, BLDX)
==========================================
  - immediate addressing BLDX $1234:
    1) load 1st operand to big register HI
    2) increment PC
    3) load 2nd operand to big register LO
    4) increment PC
    3) update Z flag (BLDX only)

  - absolute addressing BLDX [$1234]:
    1) load 1st operand to TPCA HI
    2) increment PC
    3) load 2nd operand to TPCA LO
    4) increment PC
    5) load big register HI using TPCA as address
    4) increment TPCA
    5) load big register LO using TPCA as address
    6) update Z flag (BLDX only)

Big store instructions (BSTSP, BSTX)
==========================================
  - absolute addressing BSTX [$1234]:
    1) load 1st operand to TPCA HI
    2) increment PC
    3) load 2nd operand to TPCA LO
    4) increment PC
    5) store big register HI using TPCA as address
    4) increment TPCA
    5) store big register LO using TPCA as address

JMP instruction
===============
  - absolute addressing JSR [$1234]:
    1) load 1st operand to TPCA HI
    2) increment PC
    3) load 2nd operand to TPCA LO
    4) load PC with TPCA

  - indexed addressing JSR [$1234, X]:
    1) load 1st operand to TPCA HI
    2) increment PC
    3) load 2nd operand to TPCA LO
    4) load PC with TPCA + X

  - indirect addressing JSR [[$1234]]:
    1) load 1st operand to TPCA HI
    2) increment PC
    3) load 2nd operand to TPCA LO
    4) load TPCB HI using TPCA as address
    5) increment TPCA
    6) load TPCB LO using TPCA as address
    7) load PC with TPCB

  - pre-indexed indirect addressing JSR [[$1234, X]]:
    1) load 1st operand to TPCA HI
    2) increment PC
    3) load 2nd operand to TPCA LO
    4) load TPCB HI using TPCA+X as address
    5) increment TPCA
    6) load TPCB LO using TPCA+X as address
    7) load PC with TPCB

  - indirect post-indexed addressing JSR [[$1234], X]:
    1) load 1st operand to TPCA HI
    2) increment PC
    3) load 2nd operand to TPCA LO
    4) load TPCB HI using TPCA as address
    5) increment TPCA
    6) load TPCB LO using TPCA as address
    7) load PC with TPCB + X

Conditional JMP instructions (JC, JNC, JZ, JNZ, JN, JNN, JO, JNO)
=================================================================
  - absolute addressing only JC [$1234]:
    1) check condition
  * is TRUE:
    2A) load 1st operand to TPCA HI
    3A) increment PC
    4A) load 2nd operand to TPCA LO
    5A) load PC with TPCA
  * is FALSE:
    2B) increment PC
    3B) increment PC

JSR instruction
===============
  - absolute addressing JSR [$1234]:
    1) load 1st operand to TPCA HI
    2) increment PC
    3) load 2nd operand to TPCA LO
    4) increment PC
    5) push PC LO
    6) push PC HI
    7) load PC with TPCA

  - indexed addressing JSR [$1234, X]:
    1) load 1st operand to TPCA HI
    2) increment PC
    3) load 2nd operand to TPCA LO
    4) increment PC
    5) push PC LO
    6) push PC HI
    7) load PC with TPCA + X

  - indirect addressing JSR [[$1234]]:
    1) load 1st operand to TPCA HI
    2) increment PC
    3) load 2nd operand to TPCA LO
    4) increment PC
    5) load TPCB HI using TPCA as address
    6) increment TPCA
    7) load TPCB LO using TPCA as address
    8) push PC LO
    9) push PC HI
    10) load PC with TPCB

  - pre-indexed indirect addressing JSR [[$1234, X]]:
    1) load 1st operand to TPCA HI
    2) increment PC
    3) load 2nd operand to TPCA LO
    4) increment PC
    5) load TPCB HI using TPCA+X as address
    6) increment TPCA
    7) load TPCB LO using TPCA+X as address
    8) push PC LO
    9) push PC HI
    10) load PC with TPCB

  - indirect post-indexed addressing JSR [[$1234], X]:
    1) load 1st operand to TPCA HI
    2) increment PC
    3) load 2nd operand to TPCA LO
    4) increment PC
    5) load TPCB HI using TPCA as address
    6) increment TPCA
    7) load TPCB LO using TPCA as address
    8) push PC LO
    9) push PC HI
    10) load PC with TPCB + X

RTS instruction
===============
  1) increment SP
  2) pop TPCA LO from the stack
  3) increment SP
  4) pop TPCA HI from the stack
  5) load PC with TPCA

HW interrupt ("JIR instruction")
================================
  1) set interrupt latch
  2) clear I flag
  3) set IACK
  4) push PC LO onto the stack
  5) decrement SP
  6) push PC HI onto the stack
  7) decrement SP
  8) push SR onto the stack
  9) decrement SP
  10) load PC with IV

RTI instruction
===============
  1) increment SP
  2) pop SR from the stack
  3) increment SP
  4) poop TPCA LO from the stack
  5) increment SP
  6) poop TPCA HI from the stack
  7) clear IACK
  8) load PC with TPCA