CPU Implementation Description
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The CPU is implemented as a Moore machine which consists of 3 VHDL
processes:
  1) the state advance process
  2) the transition table
  3) the output table
The state advance process is synchronously clocked by the (single) CPU clock
and asynchronously reset by the CPU reset signal. Both the transition table
and the output table are purely combinatoric logic. Notice the default
assignments outside the big CASE statement in the output table to avoid
generation of latches.

The CPU registers are separate VHDL processes each. The communication with
the control state machine is done via control signals. 
All registers are initialized to 0 during CPU reset.

The real operations (arithmetic, logic) are done in the process of the
Accumulator. Similarily inrementing PC, SP , X register, etc. is done
within the respective register's process.
The flags are updated inside the main "case - when" statement (output
table of the Moore Machine). This is done to save additional CPU cycle(s).
Consider a simple LDA instruction. The LDA instruction updates the Zero
flag and the Negative flag. Normally you would expect that the accumulator
is loaded and afterwards the flags are updated. This would (at least with
some instructions and some addressing modes) result in an additional CPU
cycle. Therefore the flags are generated in a "look-ahead" fashion  in
parallel to the efective operation.

The number of consumed cycles is different from those mentioned in the
"The Official DIY Calculator Data Book".

In case of an unknown opcode the state machine has to cycle through all
states just cusiming cycle but nothing happens.

The nRD and nWR strobes are shifted half a clock cycle. This is to
guarantee stable address and data lines during the active (rising) edge
of nRD and nWR. Since the signals cannot be shifted ahead in time the
respective signals are generated one cycle early and then delayed half
a clock cycle (clocked through a flip flop with falling edge of clock).

The nRQ line is latched synchronously with rising edge of CPU clock. It
is evaluated during state T1 (opcode fetch 1). If an interrupt is detected,
the Instruction Register is loaded with the "JIR" instruction. In consecutive
states the JIR instruction is executed just as any other instruction.