How to make a new version of the FPGA
=====================================

These are the VHDL sources for the FPGA:
  - diy_calculator.vhd ... overall design
  - clock_generator.vhd .. generates different clocks for
                           CPU, UART, keypad, LCD
  - address_decoder.vhd .. generates select signals for
                           ROM, RAM, IO, keypad, FPGA version register,
                           IRQ source register, LCD controller, user LEDs
                           register, UART, monitor RAM
  - cpu.vhd .............. the DIY Calculator CPU
  - uart.vhd ............. the UART
  - keypad_ctrl.vhd ...... the keypad controller
  - lcd_ctrl.vhd ......... the LCD access controller
  - dff8.vhd ............. an 8bit D flip flop (similar to '374), used for
                           user LEDs
  - irq_ctrl.vhd ......... a simple interrupt controller
  - spi_ctrl.vhd ......... a controller for SPI Flash access

Furthermore there is a VHDL test bench file:
  - tb_diy_calculator.vhd: overall simulation stimulus (mainly rst, clk)

Additionally you need modules for the ROM, RAM, and monitor RAM.
First delete the corresponding module (e.g. "rom.lpc") from the ispLEVER
project.
Then generate new modules:
Start the "IPexpress" program (part of the ispLEVER build environment).
For RAM and monitor RAM select "Module/Memory_Modules/EBR_Components/RAM_DQ"
from the tree view in the left pane of the IPexpress window. Type the correct
filename (without suffix) in the right pane under "File Name:". The correct
names are:
  ram ... for RAM
  mram .. for monitor RAM
Then click the "Customize" button. A new window opens.
  - In the "Address Depth" field enter the RAM size (e.g. 256 for mRAM).
    This must match with the number of address lines defined in the
    "diy_calculator.vhd" VHDL source file.
  - deselect "Enable Output Register"
  - select "Import LPC to ispLever project"
  - select "Addressed HEX" as the file format
  - click on the "..." button to launch the "File Open" dialog and select
    the appropriate memory initialization file (.mem). Although it is not
    strictly necessary to initialize RAM it is recommended to load the RAM
    with all '0'.
  - click "Generate"
    The RAM module (ram.lpc, mram.lpc) is generated and imported into ispLEVER
    (you can see ipsLEVER being busy in the background)
  - click "Close" to close the RAM configuration window.

If you want to generate the ROM module, including a new version of the
firmware, you have to proceed as follows:
  - Modify and edit the assembler source file (diy_calc.asm)
  - Assemble with the following command (assume using TASM):
       tasm -01 -i -o10 -c -f0 diy_calc.asm diy_calc.hex
    .. which means:
       -01 .. table file TASM01.TAB
       -i ... case insensitive (labels)
       -o10 . 16 bytes in one line of output file, assume Intel HEX format
       -c ... continous memory block
       -f0 .. fill empty bytes with $00
  - then generate the .mem file with the 'hex2mem' utility:
       hex2mem diy_calc
  - start IPexpress and select "Module/Memory_Modules/EBR_Components/ROM"
  - select "rom" as the file name and click "Customize" (confirm the
    "overwrite" message box)
  - as with the RAM modules select the correct size of the ROM in the
    "Address Depth" field. Again, this must match with the number of address
    lines in the "diy_calculator.vhd" VHDL source file.
  - deselect "Enable Output Register"
  - select "Import LPC to ispLever project"
  - select "Addressed HEX" as the file format
  - click on the "..." button to launch the "File Open" dialog and select
    the diy_calc.mem file you previously generated.
  - click "Generate"
    The ROM module (rom.lpc) is generated and imported into ispLEVER
  - click "Close" to close the ROM configuration window.

In ispLEVER select the FPGA chip (LFEC10E-3256C) and click "Generate PROM Data"