DIY-Calculator Hardware:Community Portal
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| The layout will somewhat resemble the layout of the (virtual) DIY Calculator with an 20x1 character LC display and a 70 keys sensor key matrix. Additionally there are connectivity means for a host PC: | The layout will somewhat resemble the layout of the (virtual) DIY Calculator with an 20x1 character LC display and a 70 keys sensor key matrix. Additionally there are connectivity means for a host PC: | ||
| - | * serial RS-232 for uploading user programs and providing a console to the DIY Calculator CPU | + | * serial (RS-232) for uploading user programs and providing a console to the DIY Calculator CPU |
| * a JTAG programming connector; this connects to the PC's parallel port and enables the user to load new designs into the FPGA | * a JTAG programming connector; this connects to the PC's parallel port and enables the user to load new designs into the FPGA | ||
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| - | Project status (19.Jul.2006): schematics completed, PCB layout work started | + | '''Project status''' (19.Jul.2006): schematics completed, PCB layout work started |
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| The FPGA design of the DIY Calculator is based on the [http://www.diycalculator.com/popup-m-phyver.shtml work] of Steven Cooper, Carl Hoggins, Bjornar Prestegard, Svein Roar Kvaale, and Dr Albert Koelmans (instructor) of the University of Newcastle Upon Tyne, England. | The FPGA design of the DIY Calculator is based on the [http://www.diycalculator.com/popup-m-phyver.shtml work] of Steven Cooper, Carl Hoggins, Bjornar Prestegard, Svein Roar Kvaale, and Dr Albert Koelmans (instructor) of the University of Newcastle Upon Tyne, England. | ||
| - | Additionally to the CPU and ROM and RAM there will be special logic for the switch matrix, for LCD output, an a UART for RS-232 communication to the PC host. | + | Additionally to the CPU and ROM and RAM there will be special logic for the switch matrix, for LCD output, an a UART for RS-232 communication to the host PC. |
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| + | '''Project status''' (19.Jul.2006): concept proved, basic integration into ispLEVER | ||
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| == ROM Monitor Project == | == ROM Monitor Project == | ||
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| + | On of the primary goals of the DIY Calculator project is to teach how computers are working on machine language level. So everyone is highly encouraged to write translate various algorithms into assembly programs for the DIY Calculator. The current virtual DIY Calculator comes with a ready-to-use environment, which includes the calculator-like user interface, a simulator, single-step debugger, and memory and register display. When translating the design to a physical one there has to be some environment. The most important functionality (and this is the only one being in scope of this project) is to upload user programs to the DIY Calculator hardware. | ||
| == Upload Utility Project == | == Upload Utility Project == | ||
Revision as of 11:04, 19 July 2006
The DIY Calculator Hardware Project consists of several sub projects:
- Creating the real hardware: a printed circuit board (PCB) with the processing chips, an LCD module, switches, and connectivity to a host computer
- Implementing the DIY Calculator CPU together with supporting functional blocks within a programmable logic chip (a so-called "Field Programmable Gate Array" - FPGA).
- Writing the firmware running on the hardware, including a ROM monitor
- Adding a software tool for communicating with the hardware (e.g. uploading user programs)
On this page you will find information about the progress of the project as well as technical details.
Contents |
Hardware Project
Block diagram of the PCB:
The layout will somewhat resemble the layout of the (virtual) DIY Calculator with an 20x1 character LC display and a 70 keys sensor key matrix. Additionally there are connectivity means for a host PC:
- serial (RS-232) for uploading user programs and providing a console to the DIY Calculator CPU
- a JTAG programming connector; this connects to the PC's parallel port and enables the user to load new designs into the FPGA
Additionally there will be sockets for external ROM/RAM chips and a large prototyping area for free use.
Download the detailed schematics from here: Image:Schematics.pdf
Project status (19.Jul.2006): schematics completed, PCB layout work started
FPGA Project
The PCB will contain an FPGA chip in the 10K-gates size-class (Lattice LFEC10E-3F256C) with a 256 pin BGA footprint. The included JTAG connector makes this a development board for general use. With ispLEVER, the FPGA development software suite from Lattice Semiconductor, the FPGA design can be altered or a completely new design can be made. The entry level version of ispLEVER (ispLEVER-Starter) can be downloaded freely from Lattice. With Lattice's ispVM System the design can be transferred via JTAG to the DIY Calculator PCB.
The FPGA design of the DIY Calculator is based on the work of Steven Cooper, Carl Hoggins, Bjornar Prestegard, Svein Roar Kvaale, and Dr Albert Koelmans (instructor) of the University of Newcastle Upon Tyne, England.
Additionally to the CPU and ROM and RAM there will be special logic for the switch matrix, for LCD output, an a UART for RS-232 communication to the host PC.
Project status (19.Jul.2006): concept proved, basic integration into ispLEVER
ROM Monitor Project
On of the primary goals of the DIY Calculator project is to teach how computers are working on machine language level. So everyone is highly encouraged to write translate various algorithms into assembly programs for the DIY Calculator. The current virtual DIY Calculator comes with a ready-to-use environment, which includes the calculator-like user interface, a simulator, single-step debugger, and memory and register display. When translating the design to a physical one there has to be some environment. The most important functionality (and this is the only one being in scope of this project) is to upload user programs to the DIY Calculator hardware.
